Using VGA cards

The Issues

When trying to get a VGA card to output the frequencies you want, using the linux kernel framebuffer, you are basically facing two issues:

Limits enforced in the driver

Most of the time, these are oversimplified limits from the vendors, probably because it's easier to say, "minimum output frequncy is X", rather than explaining how the whole cardworks.

"Bugs"

Programming the PLL pixelclock is a fairly generic problem, but the drivers are anything but generic. Even when programming cards with timings that are well within the operating range, the drivers often picks problematic PLL parameters that gives you an unstable pixelclock. It can look something like this, or this.



PLL (Phase-Locked Loop) operation, the hardware behind the pixelclock


At the start, there is the input frequency to the circuit, FOsc. This is normally generated by a Crystal Oscillator that you can see on your card, they are commonly labeled with their output frequency. Normal frequencies are 14.31 and 27.0MHz. FOsc is divided by the "Reference Divider" by a factor of Rdiv, resulting in a signal with lower frequency, FComp1.

The "Phase-Frequency Detector" (PFD), compares two signals, in this case Fcomp1 and Fcomp2. If the signals are equal, it does "nothing", if they are different it sends up/down signals to the charge pump/loop filter that results in either an increase or decrase in the control voltage fed to the VCO.

The Voltage Controlled Oscillator outputs a frequency based on the control voltage it receives, Fvco, which is split and sent to the Post Divider and the Feedback Divider.

The Post Divider, divides Fvco with a function of Pdiv, the result is the final output frequency, Fout.

The Feedback divider divides Fvco with a factor of Fdiv, resulting in Fcomp2 which is fed back to the PFD. The PFD now adjusts the control voltage fed to the VCO, until the Fcomp1=Fcomp2.

Characteristics of the dividers

To keep it simple, this plot has Fosc=1, no post divider, and plot range of 1-10 for feedback and reference.

Reference Divider

The reference divider sets the granularity of the feedback divider. The VCO frequency is FOsc/Rdiv * Fdiv. The higher the Rdiv, the more granular the Fdiv.

Feedback Divider

The feedback simply acts as a multiplier.

Post Divider

The post scales down the vco range, normally by (2^Pdiv)

Observations

Maximum Fvco is when Rdiv=minimum and Fdiv=maximum.
Mimimum Fvco is when Rdiv=maximum and Fdiv=minimum.










A simple example would be to disable the dividers, meaning FComp1=Fosc. Since there is no Fdiv, Fvco=Fcomp2. The PFD adjusts the VCO's control voltage until Fcomp1=Fcomp2, when this happens the frequency is "locked", resulting in FVco=Fosc=FOut. If the VCO starts to drift in either direction, the PFD will detect this trough FComp2, and correct this with the VCO control voltage.

A slightly more intreesting scenario is introducting FDiv=2, which will cause the PFD to increase to VCO control voltage until Fvco=2*Fcomp2 (since Fcomp2 is divided by 2), giving you an FVco equal to 2*FOsc. The generic equation with the post-divider looks something like this:

The operating frequency of the VCO is simply the equation above, withouth the post-divider.


In general the different dividers is referenced as Rdiv=M, Fdiv=N, and Pdiv=P - but as with most technical things, someone decided to be a smartass and make it difficult and references Rdiv=N and Fdiv=M.









Notes

Texas-Instruments, M=Rdiv, N=Fdiv, P=Pdiv
Altera: N=Rdiv, M=Fdiv, C=Pdiv

14.31818 MHz is 4x the subcarrier frequency for NTSC.
"For optimized jitter performance, keep divider M as small as possible"

Notes
Output Swing
Output Frequency
PLL lock range
When compiling your kernel, these are found in Device Drivers --->, Graphics support --->,




page was last modified: March 18 2007 23:30 CET